The present invention is directed to an information processing apparatus incorporating micro program control method, more specifically to a micro program control method and apparatus thereof for data processing with microprogram control, which allows high speed fetching of micro instructions from control storage without increasing the program capacity of microprograms.
A first example of the Prior Art technology performs micro program control, which has a field for specifying the branch target address of next clock cycle (referred to as a cycle, hereinbelow) by a micro instruction and a field for controlling a processor.
Now referring to FIGS. 5 through 8 an embodiment in accordance with the first example of the Prior Art technology and the execution procedure will be described.
Referring at first to FIG. 6, there is shown a format of micro instruction in accordance with first example of the Prior Art technology, which instruction comprises a page address field 600 of branch target of the micro instruction, an end judgment field 601 for determining whether or not the micro program terminates in next cycle, a branch condition field 602 for use in the branch judgment, and a control field 603 for controlling the execution in next cycle. In first example of the Prior Art technology, a pair of micro instructions composes a page.
FIG. 5 is a block diagram of a micro program controller embodied by the first example of the Prior Art technology. This controller comprises an instruction fetch unit 50, a read/branch unit 51 for reading and branching micro instructions, and an execution unit 52 for executing computations such as additions and data shifts. The execution unit 52 includes ALUs, decoders and registers.
The an instruction fetch unit 50 comprises a start address register 510 for storing the start address of a micro program. The read/branch unit 51 is constituted of an end judgment circuit 531 for generating a termination signal of micro program by referring to the end judgment field 601 of the micro instruction, an address selector 520 for determining whether to start, continue, or terminate a micro program by referring to the termination signal of the micro program, an address register 511 for storing the page address of micro instruction, a control storage 530 for storing micro instructions, a branch judgment circuit 532 for determining whether to branch or not by referring to both the micro instruction read out during the immediately preceding cycle and the result of execution of the previous cycle, a bank selector 521 to which one instruction selected from two micro instructions read out in accordance with the branch judgment signal is output, and a data register 512 for storing the branch condition field 602 of micro instruction and the control field 603. The control storage 530 has two banks, namely bank 0 and bank 1, specified by the same address, and stores a micro instruction page. As have been described above one page is of the size of two micro instructions.
Next referring to the timing chart shown in FIG. 7 and to the flow chart shown in FIG. 8, the execution procedure of a micro program control embodied by the first example of Prior Art technology.
In cycle (C-1), a start address A10 of a micro program stored in the start address register 510 in the instruction fetch unit 50 is transferred to the read/branch unit 51. The start address A10 is input to the address selector 520 and stored in the address register 511 after the transfer.
In cycle (C0), the page address of the control storage 530 is specified by the start address A10 of the micro program stored in the address register 511, to read out a micro instruction M100 from the bank 0 and another micro instruction M101 from the bank 1. The bank selector 521 selects either of two micro instructions M100 and M101 read out from the banks to start a branch operation B10. In the flow chart (FIG. 8), the micro instruction M100 read out from the bank 0 is selected at the branch operation B10. The page address field A20 of the selected micro instruction M100 is input to the address selector 520 and stored in the address register 511, while the branch condition field (not shown) and control field i100 in the micro instruction M100 selected by the bank selector 521 are stored in the data register 512.
In cycle (C1), as similar to the preceding cycle (C0), the page address A20 of the control storage 530 is selected for reading out and branching the micro instructions M200 and M201. The control field i100 of the micro instruction M100 stored in the data register 512 is transferred to the execution unit 52 to start executing operations. In the procedure shown in this flow chart (FIG. 8), for the sake of facilitating the understanding of the illustrated procedure, the branching selects alternately bank 0 and bank 1. As the result of foregoing execution, the micro instruction controls the execution unit in the following order: i100 (cycle C1), i201 (cycle C2), i310 (cycle C3), i421 (cycle C4).
In a second example of the Prior Art technology a micro instruction having one field of branched target address following Nth cycle (where Nxe2x89xa72) and another field for controlling the execution following Nth cycle (where Nxe2x89xa72) controls the micro program. This technology has been devised for accelerating said first technology, as disclosed in the U.S. Pat. No. 4,494,195.
Now referring to FIGS. 9 through 12 an embodiment in accordance with the second Prior Art technology (in case of N=2) and the execution procedure thereof will be described below.
FIG. 10 shows an exemplary format of a micro instruction in accordance with the second Prior Art technology, with N=2, which contains a field of page address following the next cycle 1000, a field of end judgment following the next cycle 1001 for use in determining whether the micro program terminates by second cycles, a field of branch condition following the next cycle 1002 for use in the branch judgment by the cycle following the next, and a field of control following the next cycle 1003 for use in controlling the execution in the cycle following the next. In this second Prior Art technology a set of four micro instructions composes a page.
FIG. 9 shows a block diagram of a micro program controller embodied by the second Prior Art technology, with N=2. This controller unit, as similar to preceding first technology, comprises an instruction fetch unit 90, a read/branch unit 91, and an execution unit 92.
In second technology of the Prior Art, where N=2, in order to obtain the same micro program control as first technology, a start address should be fetched at the beginning of the micro program, in addition to two micro instructions to be executed in the cycle following the next (for bank 0 and bank 1, respectively). The instruction fetch unit 90 thus comprises a start address register of micro program 910, a second cycle micro instruction register (bank 0) 911 for use in storing second cycle micro instruction (bank 0), and another second cycle micro instruction register (bank 1) 912 for use in storing second cycle micro instruction (bank 1).
The read/branch unit 91 comprises a bank selector 920 for selecting either one of second cycle micro instruction register 911 (for bank 0) or second cycle micro instruction register 912 (for bank 1), an end judgment circuit 931, an address selector 921, an address register 913, a control storage 930 including 4 banks constituted of bank 00, bank 01, bank 10, and bank 11, a branch judgment circuit 932, a bank selector 922 for selecting either one of micro instruction read from bank 00 and bank 10 of the control storage 930, another bank selector 923 for selecting either one of micro instruction read from bank 01 and bank 11 of the control storage 930, another bank selector 920 for selecting one micro instruction from within micro instructions selected by the bank selector 922, bank selector 923 and bank selector 924, and a data register 914.
Next, the operation and execution procedure of the micro program controller embodied by the second technology will be described below with reference to the timing chart shown in FIG. 11 and the flow chart shown in FIG. 12. In the second Prior Art technology, since read/branch is executed for two cycles, a read/branch (for even cycle) for starting read out of the control storage 930 in an even cycle and another read/branch (for odd cycle) for starting read out of the control storage 930 in an odd cycle are executed in a pipeline manner.
Now the read/branch (for odd cycle) will be described in greater details. In cycle (C-1) the page address field A20 of micro program stored in the register of micro program start address resister 910 in the instruction fetch unit 90 is transferred to the read/branch unit 91. Thereafter, the page address A20 is input to the address selector 921 and then stored in the address register 913.
In cycle (C0), a page in the control storage 930 is specified by the page address A20 of the micro program stored in the address register 913 to read out four micro instructions M200 (from bank 00), M201 (from bank 01), M210 (from bank 10) and M211 (from bank 11), which will be executed in the cycle following the next (C2). Either the micro instruction M200 read out from the bank 00 or micro instruction M210 read out from the bank 10 is selected by the bank selector 922, while at the same time either the micro instruction M201 read out from the bank 01 or the micro instruction M211 read out from the bank 11 is also selected by the bank selector 923 in parallel, so as to perform a branch operation B10. In the flow chart (FIG. 12), a branch operation B10 selects a pair of micro instruction M200 read out from the bank 00 and micro instruction M201 read out from the bank 01. Depending on the design of apparatus, the branch operation B10 may be done in the next cycle (C1).
In cycle (C1), the bank selector 924 selects a micro instruction M201 from a pair of two micro instructions M200 and M201 selected in the branch operation B10 of the preceding cycle (C0) (branch operation B20). The field A41 of page address following the next cycle of the selected micro instruction M201 is input into the address selector 921 and then stored to the address register 913. The field of branch condition following the next cycle and the control field following the next cycle (i201) of the selected micro instruction (not shown) selected by the bank selector 924 are stored into the data register 914.
In cycle (C2), in addition to a read out of micro instructions as similar to cycle (C0), control field following the next cycle (i201) stored in the data register 914 is transferred to the execution unit 92 to start execution. In a similar manner, the read/branch (for even cycle) and execution will be performed. In the flow chart (FIG. 12), the micro instruction selected by the read/branch (for even cycle) controls the execution unit in the following order: i201 (cycle C2), i421 (cycle C4).
Now the read/branch operation (for odd cycle) will be described below in greater details. Two micro instructions M100 and M101 stored in the second cycle micro instruction register 911 (bank 0) and the second cycle micro instruction register 912 (bank 1) in the instruction fetch unit 90 are transferred to the read/branch unit 91 in cycle (C0). After that, one micro instruction M100 is selected by the bank selector 920 from these two micro instructions (branch operation B10) The address following the next cycle field A30 of the micro instruction M100 selected by the bank selector 920 is input to the address selector 921 and stored in the address register 913. At the same time, the branch condition field (not shown) and the control field (i100) of the micro instruction M100 selected by the bank selector 920 will be input to the bank selector 924 and stored in the data register 914.
In cycle (C1), a read/branch operation is performed as similar to the cycle (C0) of read/branch operation (for even cycle), as well as the control field i100 stored in the data register 914 is transferred to the execution unit 92 to start execution. In a similar manner, the read/branch operation (for odd cycle) and execution will be performed. In the flow chart (FIG. 12), the micro instruction selected by the read/branch (for odd cycle) controls the execution unit in the following order: i100 (cycle C1), i310 (cycle C3).
As a result, when the read/branch operation (for even cycle) and read/branch operation (for odd cycle) performed in a pipeline basis are combined, the micro instruction controls the execution unit 92 in the following order: i100 (cycle C1), i201 (cycle C2), i310 (cycle C3), i421 (cycle C4). One may be appreciated that the execution procedure is the same as the first Prior Art technology.
In recent years, the access time of memory and the line delay in the signal transfer are the major factors limiting the operation frequency of a microprocessor.
In the micro program control in accordance with the first Prior Art technology a micro instruction possesses the field of branch target address for the next cycle. This may cause a disadvantage that the processing frequency may not be so increased, because the establishment of address of a micro instruction, comprised of a plurality of operations such as a read out of the micro instruction from the control storage, a selection of micro instruction depending on a branch condition, long distance transfer of the branch target address, should be done within a cycle.
In the micro program control in accordance with the second Prior Art technology the micro instruction possesses the branch target address of Nth cycle (Nxe2x89xa72) after the read out cycle of the micro instruction and the field for controlling execution in Nth cycle (Nxe2x89xa72). In this method the disadvantage in relation to the executable frequency is remedied by splitting the decision of address of micro instruction as performed in the first Prior Art technology into Nth cycles (Nxe2x89xa72).
The second Prior Art technology may suffer from the disadvantage that the amount of memory required for storage of micro program will be increased to (Nxe2x88x921) th power folds of 2, because the number of micro instructions to be read out at once from the control storage is Nth power of 2.
Accordingly, the object of the present invention is to provide a micro program control method and apparatus thereof, which may overcome the problem of working frequency in the first Prior Art technology and the problem of amount of memory for storing micro programs in the second Prior Art technology.
In order to achieve the above described object, the present invention makes use of a high speed micro program control method for specifying the branch target address following Nth cycle (Nxe2x89xa72), as disclosed in the second Prior Art technology (reference should be made to the U.S. Pat. No. 4,494,195), for reading out two micro instructions at once having micro instruction format with the (Nxe2x88x921) th power of 2 of fields of the branch target address in following Nth cycle, and a field for controlling the next cycle execution.
More specifically, the present invention comprises following means (1) through (3):
(1) a field for specifying a branch target address at Nth (Nxe2x89xa72) cycle after the read out cycle of the micro instruction or a field for determining the end of micro program at Nth (Nxe2x89xa72) cycle,
and a micro instruction comprised of a field for controlling the next cycle execution are used for performing in parallel the control of determination of addresses in succeeding Nth cycle and the execution control in the next cycle.
(2) for data processing under the micro instruction control that reads out M micro instructions (Mxe2x89xa72) from one single address to perform the execution of one instruction selected therefrom, a micro instruction comprising (Nxe2x88x921) th power of M of fields for specifying the branch target address in following Nth (Nxe2x89xa72) cycle after the read out cycle of micro instruction, (Nxe2x88x921) th power of M of fields for determining the termination of micro program in Nth (Nxe2x89xa72) cycle, a field for controlling the execution of the next cycle, is used so as to perform controls substantially identical to the means (1) above, even in case in which there are M branch targets.
(3) for data processing under the micro instruction control that reads out M micro instructions (Mxe2x89xa72) from one single address to perform the execution of one instruction selected therefrom, if a micro program is split into a plurality of blocks,
a micro instruction comprising (Nxe2x88x921) th power of M of fields for specifying the branch target address offset within the block in the following Nth (Nxe2x89xa72) cycle after the read out cycle of micro instruction, (Nxe2x88x921) th power of M of fields for determining the termination of micro program at the following Nth (Nxe2x89xa72) cycle, a field for specifying the branch target block address following Nth cycle (Nxe2x89xa72), and a field for controlling the execution of the next cycle, is used to perform control such that the field length (number of bits) for specifying the branch target address can be less than the methods (1) and (2) above.
Additional objects and advantages of the invention will be set forth in part in the description which follows and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and attained by means of the instrumentalities and combinations particularly pointed out in the appended claims.